ADC 1000 Dokumentacja

ADC12D1000RF, ADC12D1600RFADC12D1600/1000RF 12-Bit, 3.2/2.0 GSPS RF SamplingADCData ManualPRODUCTION DATA information is current as of publication dat

GNDVA100 k:GNDVA100 k:GNDVA50 k:GNDVAGNDVAADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.comTable 2-2. Control and Status Ball

VAGNDGNDVA100 k:ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013Table 2-2. Control and Status Balls (continued)Ball No. Name

VDRDR GND+-+-VDRDR GND+-+-ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.comTable 2-3. Power and Ground Balls (continued)Ball

VDRDR GND+-+-VDRDR GND+-+-ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013Table 2-4. High-Speed Digital Outputs (continued)B

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.com3 Electrical Specifications3.1 Absolute Maximum Ratings(1)(2)Supply Voltage

I / OGNDVATO INTERNALCIRCUITRYADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013Operating Ratings(1)(2)(continued)Common Mode

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.com3.5 Converter Electrical CharacteristicsDynamic Converter Characteristics(1)

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013Converter Electrical CharacteristicsDynamic Converter Characteristics(1)(con

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.comConverter Electrical CharacteristicsDynamic Converter Characteristics(1)(con

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 20133.6 Converter Electrical CharacteristicsAnalog Input/Output and Reference Ch

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013ADC12D1600/1000RF 12-Bit, 3.2/2.0 GSPS RF Sampling ADCCheck for Samples: ADC

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.com3.7 Converter Electrical CharacteristicsI-Channel to Q-Channel Characteristi

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 20133.10 Converter Electrical CharacteristicsDigital Control and Output Pin Char

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.com3.11 Converter Electrical CharacteristicsPower Supply CharacteristicsADC12D1

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013Converter Electrical CharacteristicsAC Electrical Characteristics (continued

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.com3.13 Converter Electrical CharacteristicsSerial Port InterfaceADC12D1600RF A

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 20134 Specification DefinitionsAPERTURE (SAMPLING) DELAY is the amount of delay,

VD+VD-VOS GND½×VOD = | VD+ - VD- |½×VOD VD-VD+ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.comFigure 4-1. LVDS Output Signal

ACTUAL POSITIVEFULL-SCALETRANSITION-VIN/2ACTUAL NEGATIVEFULL-SCALE TRANSITION1111 1111 1111 (4095)1111 1111 1110 (4094)1111 1111 1101 (4093)MID-SCALET

tODtADSample NDQSample N+1DQSample N-1VINQ+/-CLK+DCLKQ+/-(0° Phase)DQ Sample N-35Sample N-36tOSKSample N-34 Sample N-33 Sample N-37tODtADSample NDISam

tODtADSample NDISample N+1DISample N-1VINQ+/-CLK+DCLKQ+/-(0° Phase)DQ, DI Sample N-35.5, N-35tOSKSample N-34.5, N-34 Sample N-33.5, N-33 Sample N-36.5

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 20131.3 DescriptionThe 12-bit 3.2/2.0 GSPS ADC12D1600/1000RF is an RF-sampling G

SCLK18 924Single Register AccessSCSSDICommand FieldMSBLSBData FieldtSSUtSHtSCStHCStHCSSDO read mode)MSBLSBData FieldtBSUHigh Z High ZCalRunPOWER SUPPL

0 4095-0.75-0.50-0.250.000.250.500.75DNL (LSB)OUTPUT CODE0 4095-0.75-0.50-0.250.000.250.500.75DNL (LSB)OUTPUT CODE-50 0 50 100-1.0-0.50.00.51.0INL (LS

0 1000 2000 3000678910ENOBINPUT FREQUENCY (MHz)NON-DES MODEDES MODE0.75 1.00 1.25 1.50 1.75678910ENOBVCMI(V)NON-DES MODEDES MODE-50 0 50 100678910ENOB

-50 0 50 100-80-70-60-50-40THD (dBc)TEMPERATURE (°C)NON-DES MODEDES MODE1.8 1.9 2.0 2.1 2.2-80-70-60-50-40THD (dBc)VA(V)NON-DES MODEDES MODE1.8 1.9 2.

0 1000 2000 3000-100-90-80-70-60-50-40CROSSTALK (dBFS)AGGRESSOR INPUT FREQUENCY (MHz)NON-DES MODE0 1000 2000 3000-100-90-80-70-60-50-40CROSSTALK (dBFS

0 250 500 750 10002.02.53.03.54.04.55.0POWER (W)CLOCK FREQUENCY (MHz)DEMUX MODENON-DEMUX MODE0 1000 2000 3000 4000-15-12-9-6-30SIGNAL GAIN (dB)INPUT F

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.com6 Functional DescriptionThe ADC12D1600/1000RF is a versatile A/D converter w

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013Table 6-1. Non-ECM Pin SummaryPin Name Logic-Low Logic-High FloatingDedicate

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.com6.2.1.4 Calibration Pin (CAL)The Calibration (CAL) Pin may be used to execut

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013To use this feature in ECM, use the Configuration Registers (Addr: 3h and Bh

0 1 2 3 4-100-90-80-70-60-50-40IMD3(dBFS)FREQUENCY (GHz)-7 dBFS-10 dBFS-13 dBFS-16 dBFSADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 201

SDISDOR/W1 0 A3 A2 A1 A0 XD14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D1521 43 65 87 109 1211 1413 1615 1817 2019 2221 2423 25*Only required to b

SDISDOR/W1 0 A3 A2 A1 A0 X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D021 43 65 87 109 1211 1413 1615 1817 2019 2221 2423 25SCLKSCSbADC12D100

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.comTable 6-4. Features and Modes (continued)Control PinFeature Non-ECM ECM Defa

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 20136.3.1.4 DES/Non-DES ModeThe ADC12D1600/1000RF can operate in Dual-Edge Sampl

DataDCLK 0° ModeDCLK 90° ModeADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.com6.3.1.6 Sampling Clock Phase AdjustThe sampling

DataDCLK SDR RisingDCLK SDR FallingADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013Figure 6-4. SDR DCLK-to-Data Phase Relati

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.com6.3.2.6 Test Pattern ModeThe ADC12D1600/1000RF can provide a test pattern at

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 20136.3.2.7 Time StampThe Time Stamp feature enables the user to capture the tim

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.comThe power-on calibration will be not be performed if the CAL pin is logic-hi

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 20135. Continue with normal operation.To write calibration values to the SPI, do

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20AGND V_A SDO TPM NDM V_A GND V_E GND_E DId0+ V_DR DId3+ GND_DR DId6+ V_DR DId9+ GND_DR DId11+ DId11-

ADC12D1600/1000RFVINI+50: SourceVINI-1:1 BalunCcoupleCcouple100:VINQ+VINQ-100:CcoupleCcoupleADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRI

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013Table 6-9. Unused Analog Input RecommendedTerminationMode Power Coupling Rec

ADC12D1600/1000RFVIN+50: SourceVIN-1:2 BalunCcoupleCcouple100:VIN+VIN-VCMOADC12D1600/1000RFCcoupleCcoupleADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011

CLK+CLK-ADC12D1600/1000RFCcoupleCcoupleADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 20136.4.2 THE CLOCK INPUTSThe ADC12D1600/

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.com6.4.2.5 CLK JitterHigh speed, high performance ADCs such as the ADC12D1600/1

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 20136.4.3.3 Terminating Unused LVDS Output PinsIf the ADC is used in Non-Demux M

CLKMasterADC12D1600/1000RFSlave 1ADC12D1600/1000RFCLKCLKCLKRCLKRCLKRCOut1RCOut2DCLKDCLK DCLKRCLKRCOut1RCOut2RCOut1RCOut2Slave 2ADC12D1600/1000RFADC12D

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 20136.4.5 SUPPLY/GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS6.4.5.1 Power Plan

Cross Section LineIC DieNot to ScaleMold CompoundCopper Heat SlugSubstrate4JC_24JC_11.9V ADC MainSwitching RegulatorLinear RegulatorVDRVEVAVTCHV or Un

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013The center ground balls should be soldered down to the recommended ball pads

VAAGNDVAAGND100VAAGNDVAAGND100VBIAS50k50k50kVAAGNDVAAGND50kControl from VCMOVCMO100ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www

Power-on CalibrationOn-command CalibrationPower to ADCCalibrationCalDlyPull-up/down resistors set Control PinsADC output validADC12D1000RF, ADC12D1600

FPGA writes Control PinsPower-on CalibrationOn-command CalibrationPower to ADCCalibrationCalDlyFPGA writes Control PinsPower-on CalibrationOn-command

VADCLK19001710timemV66063514905203001210Slope = 1.22V/msADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.comFigure 6-15. Supply

LM95213100 pFADC12D1600/1000RFIRIE = IF100 pF76D1+D2+5D-FPGAIRIE = IFADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013In the

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.comTable 6-13. Balun RecommendationsBalun BandwidthMini Circuits TC1-1- 4.5 - 3

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013Bit 12 TPM: Test Pattern Mode. When this bit is set to 1b, the device will c

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.com1000 0000 0000 22.51111 1111 1111 45Table 6-18. I-channel Full Scale Range A

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013Bits 15:0 Reserved. Must be set as shown.Table 6-22. DES Timing AdjustAddr:

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.comTable 6-26. Q-channel Full-Scale Range AdjustAddr: Bh (1011b) POR state: 400

ADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013Table 6-29. AutoSync(1)Addr: Eh (1110b) POR state: 0003hBit 15 14 13 12 11 1

VAVAGNDGNDTdiode_PTdiode_NGNDVAVGNDVAVVAGNDGNDVA200k8 pFVCMOEnable AC CouplingADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 20

ADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.comRevision HistoryNOTE: Page numbers for previous revisions may differ from pa

PACKAGE OPTION ADDENDUMwww.ti.com7-Mar-2015Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEco

PACKAGE OPTION ADDENDUMwww.ti.com7-Mar-2015Addendum-Page 2continues to take reasonable steps to provide representative and accurate information but ma

MECHANICAL DATANXA0292Awww.ti.com

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherch

GNDVAGNDVAVAA GND-+100:100:VAAGNDVAAGND100VBIAS50k50kADC12D1000RF, ADC12D1600RFSNAS519G –JULY 2011–REVISED APRIL 2013www.ti.comTable 2-1. Analog Front

GNDVAGNDVAGNDVA50 k:VAGNDGNDVAADC12D1000RF, ADC12D1600RFwww.ti.comSNAS519G –JULY 2011–REVISED APRIL 2013Table 2-2. Control and Status Balls (continued