ADC 6 Dokumentacja Pobierz pdf (Strona 5)

ADC12D1800RF

www.ti.com

SNAS518I –JULY 2011–REVISED JANUARY 2014

List of Figures

2-1 ADC12D1800RF Non-DES Mode IMD

......................................................................................... 9

2-2 ADC12D1800RF DES Mode FFT.............................................................................................. 10

2-3 ADC12D1800RF Connection Diagram ........................................................................................ 10

4-1 LVDS Output Signal Levels..................................................................................................... 31

4-2 Input / Output Transfer Characteristic ........................................................................................ 33

4-3 Clocking in 1:2 Demux Non-DES Mode*...................................................................................... 33

4-4 Clocking in Non-Demux Non-DES Mode*..................................................................................... 33

4-5 Clocking in 1:4 Demux DES Mode*............................................................................................ 34

4-6 Clocking in Non-Demux Mode DES Mode*................................................................................... 34

4-7 Data Clock Reset Timing (Demux Mode) ..................................................................................... 35

4-8 Power-on and On-Command Calibration Timing............................................................................. 35

4-9 Serial Interface Timing........................................................................................................... 35

6-1 Serial Data Protocol - Read Operation ........................................................................................ 46

6-2 Serial Data Protocol - Write Operation ........................................................................................ 46

6-3 DDR DCLK-to-Data Phase Relationship ...................................................................................... 50

6-4 SDR DCLK-to-Data Phase Relationship ...................................................................................... 50

6-5 Driving DESIQ Mode............................................................................................................. 56

6-6 AC-coupled Differential Input ................................................................................................... 57

6-7 Single-Ended to Differential Conversion Using a Balun..................................................................... 57

6-8 Differential Input Clock Connection ............................................................................................ 58

6-9 AutoSync Example............................................................................................................... 61

6-10 Power and Grounding Example ................................................................................................ 63

6-11 HSBGA Conceptual Drawing ................................................................................................... 63

6-12 Power-on with Control Pins set by Pull-up / down Resistors ............................................................... 66

6-13 Power-on with Control Pins set by FPGA pre Power-on Cal ............................................................... 66

6-14 Power-on with Control Pins set by FPGA post Power-on Cal.............................................................. 66

6-15 Supply and DCLK Ramping..................................................................................................... 67

6-16 Typical Temperature Sensor Application...................................................................................... 68

1 2 3 4 5 6 7 8 9 10 ... 79 80

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ADC 6 Dokumentacja Strona 5