ADC and 3 Doubler Arkusz Danych

REV. 1.6 FS98O22-DS-16_EN MAY 2014Datasheet FS98O22 8-bit MCU with 4k program EPROM, 256-byte RAM, 1 low noise OPAMP, 8-ch 14-bit ADC, 4 × 20

FS98O22 Rev. 1.6 10/146 1. Device Overview The FS98O22 is a CMOS 8-bit single chip microcontroller(MCU) with embedded a 4kx16 bits one-time p

FS98O22 Rev. 1.6 100/146 10. Analog Function Network Please see Figure 10-1. FS98O22 Analog Function Network has 2 main functions: Low Noise

FS98O22 Rev. 1.6 101/146 Table 10-1 analog function network register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit

FS98O22 Rev. 1.6 102/146 Register ADOH at address 10H Property R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ADOH ADO [15:8] Bit7 Bit0 Register ADOL

FS98O22 Rev. 1.6 103/146 Register ADOLL at address 12H property R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ADOLL Extra ADC output register Bit7 Bi

FS98O22 Rev. 1.6 104/146 Register PCK at address 15H property U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 PCK -- S_CH1CK [1:0] -- -- Bit7

FS98O22 Rev. 1.6 105/146 Register NETA at address 18H property R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NETA SINL[1:0] SINH[2:0] S

FS98O22 Rev. 1.6 106/146 Register NETB at address 19H property U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NETB SOP1N[1:0] SVRL[1:0] S

FS98O22 Rev. 1.6 107/146 Register NETC at address 1AH property R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 NETC SREFO ADG[1:0] ADEN AZ

FS98O22 Rev. 1.6 108/146 Register NETD at address 1BH property U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 NETD OP1EN SOP1P[2:0] Bi

FS98O22 Rev. 1.6 109/146 10.1. Analog to Digital Converter (ADC) : Please see Figure 10-2. ADC Module contains 3 main functions – Low Pass Fi

FS98O22 Rev. 1.6 11/146 1.6. Applications z Sensor or transducer measurement applications. z Electronic kitchen scale, personal scale. z Di

FS98O22 Rev. 1.6 110/146 Table 10-2 ADC function register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bi

FS98O22 Rev. 1.6 111/146 Table 10-5 INH selection table SFTA[1:0] INH (ADC positive input port signal) 00 FTB 01 FTIN 10 AIN2 11 AIN3 5. Se

FS98O22 Rev. 1.6 112/146 Table 10-9 SVRL selection table SVRL[1:0] VRL (ADC reference voltage negative input) 00 AGND 01 AIN1 10 AIN2 11 VR2P

FS98O22 Rev. 1.6 113/146 10.2. OPAMP : OP1 Table 10-12 FS98O22 OPAMP register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4

FS98O22 Rev. 1.6 114/146 Table 10-15 chopper mode selection table S_CH1CK[1:0] OPAMP chopper mode (input operation) 00 +Offset 01 -Offset 10

FS98O22 Rev. 1.6 115/146 11. ADC Application Guide The ADC used in FS98O22 is a ∑-Δ ADC with fully differential inputs and fully differential

FS98O22 Rev. 1.6 116/146 To get a correct ADC result, Doff(ADC input offset digital output) should be deducted from the Dout. The instruction

FS98O22 Rev. 1.6 117/146 12. Low Noise Operation Amplifier Guide The input noise of CMOS OPAMP is generally much larger than the one of a Bip

FS98O22 Rev. 1.6 118/146 12.2. Differential Amplifier Measurement of differential signal is often used in bridge sensor applications. As sh

FS98O22 Rev. 1.6 119/146 13. LCD Driver FS98O22 embeds a LCD driver. The control signal are COM1~COM4 and SEG1~SEG12. The user could set t

FS98O22 Rev. 1.6 12/146 1.8. Pin Configuration Figure 1-1 FS98O22 pin configuration FORTUNE' Properties

FS98O22 Rev. 1.6 120/146 The LCD frame frequency could be setup by setting the LCDCKS[1:0] register flags. FS98O22 divides the LCD Module inpu

FS98O22 Rev. 1.6 121/146 Figure 13-3 LCD duty mode working cycle LCDCK 1/4 duty COM1 COM2 COM3 COM4 1/3 duty COM1 COM2 COM3 COM4 1/2 duty COM1

FS98O22 Rev. 1.6 122/146 FS98O22 LCD driver has 3 voltage bias ports, such as V1, V2 and V3, and 2 kinds of power mode: 1/3 bias and 1/2 bias.

FS98O22 Rev. 1.6 123/146 z 1/2 bias power system (Please see Figure 13-6 and 13-17) Figure 13-6 1/2 bias LCD power system circuit connection

FS98O22 Rev. 1.6 124/146 Table 13-3 FS98O22 LCD driver register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi

FS98O22 Rev. 1.6 125/146 Register LCD2 at address 41H property R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X LCD2 SEG4 [3:0] SEG3 [3:0] Bi

FS98O22 Rev. 1.6 126/146 Register LCD4 at address 43H property R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X LCD4 SEG8 [3:0] SEG7 [3:0] Bi

FS98O22 Rev. 1.6 127/146 Register LCD6 at address 45H property R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X LCD6 SEG12 [3:0] SEG11 [3:0]

FS98O22 Rev. 1.6 128/146 Register LCDENR at address 54H property R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 LCDENR LCDCKS [1:0] LCDEN

FS98O22 Rev. 1.6 129/146 Table 13-4 LCD driver register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit

FS98O22 Rev. 1.6 13/146 1.9. Pin Description Table 1-2 FS98O22 pin description Name In/Out Pin No Description VPP P 5 Programming Power

FS98O22 Rev. 1.6 130/146 Table 13-8 LCD frame frequency selection table LCDCKS [1:0] LCD frame frequency (LCDCK) 00 LCD Input clock Frequency

FS98O22 Rev. 1.6 131/146 14. Halt and Sleep Modes FS98O22 supports low power working mode. When the user want FS98O22 to do nothing and just

FS98O22 Rev. 1.6 132/146 Instruction Set The FS98O22 instruction set consists of 37 instructions. Each instruction could be converted to 16-

FS98O22 Rev. 1.6 133/146 Note:  f: memory address (00h ~ 7Fh).  W: work register.  k: literal field, constant data or label.  d: destin

FS98O22 Rev. 1.6 134/146 14.2. Instruction Description (By alphabetically) ADDLW Add Literal to W Syntax ADDLW k 0 ≤ k ≤ FFh Operation [W] ←

FS98O22 Rev. 1.6 135/146 ADDWFC Add W, f and Carry Syntax ADDWFC f, d 0 ≤ f ≤ FFh d ∈ [0,1] Operation [Destination] ← [f] + [W] + C Flag Affec

FS98O22 Rev. 1.6 136/146 BCF Bit Clear f Syntax BCF f, b 0 ≤ f ≤ FFh 0 ≤ b ≤ 7 Operation [f<b>] ← 0 Flag Affected None Description Bi

FS98O22 Rev. 1.6 137/146 CALL Subroutine CALL Syntax CALL k 0 ≤ k ≤ 1FFFh Operation Push Stack [Top Stack] ← PC + 1 PC ← k Flag Affected Non

FS98O22 Rev. 1.6 138/146 DECF Decrement f Syntax DECF f, d 0 ≤ f ≤ 255 d ∈ [0,1] Operation [Destination] ← [f] -1 Flag Affected Z Description

FS98O22 Rev. 1.6 139/146 INCF Increment f Syntax INCF f, d 0 ≤ f ≤ FFh d ∈ [0,1] Operation [Destination] ← [f] +1 Flag Affected Z Descripti

FS98O22 Rev. 1.6 14/146 1.10. Functional Block Diagram Figure 1-2 FS98O22 function block FORTUNE' Properties For Reference Only

FS98O22 Rev. 1.6 140/146 IORWF Inclusive OR W with f Syntax IORWF f, d 0 ≤ f ≤ FFh d ∈ [0,1] Operation [Destination] ← [W] | [f] Flag Affected

FS98O22 Rev. 1.6 141/146 RETFIE Return from Interrupt Syntax RETFIE Operation [Top Stack] => PC Pop Stack 1 => GIE Flag Affected None

FS98O22 Rev. 1.6 142/146 RRF Rotate right [f] through Carry Syntax RRF f, d 0 ≤ f ≤ FFh d ∈ [0,1] Operation [Destination<n-1>] ← [f<

FS98O22 Rev. 1.6 143/146 SUBWF Subtract W from f Syntax SUBWF f, d 0 ≤ f ≤ FFh d ∈ [0,1] Operation [Destination] ← [f] – [W] Flag Affected C,

FS98O22 Rev. 1.6 144/146 XORLW Exclusive OR literal with W Syntax XORLW k 0 ≤ k ≤ FFh Operation [W] ← [W] XOR k Flag Affected Z Description

FS98O22 Rev. 1.6 145/146 15. Package Information 15.1. Package Outline Figure 15-1 FS98O22 package outline FORTUNE' Properties For Ref

FS98O22 Rev. 1.6 146/146 15.2. Package Outline(3.2mm QFP100) Figure 15-2 FS98O22 3.2mm QFP100 package outline 16. Revision History Ver.

FS98O22 Rev. 1.6 15/146 There are 5 kinds of functional blocks in the Function Block Diagram, described as table 1-3: Table 1-3 FS98O22 main

FS98O22 Rev. 1.6 16/146 1.11. CPU Core Figure 1-3 FS98O22 CPU core function block The “CPU Core Block Diagram” shown in Section 1.11 mainly

FS98O22 Rev. 1.6 17/146 Table 1-4 FS98O22 CPU core block diagram description table Items Sub Items Description Registers Program Counter Th

FS98O22 Rev. 1.6 18/146 1.12. Clocking Scheme/Instruction Cycle One Instruction cycle (CPU cycle) includes 4 steps and the CPU could process

FS98O22 Rev. 1.6 19/146 2. Electrical Characteristics 2.1. Absolute Maximum Ratings Table 2-1 FS98O22 absolute maximum rating table Paramete

FS98O22 Rev. 1.6 2/146 Fortune Semiconductor Corporation 富晶電子股份有限公司 23F., No.29-5,Sec. 2, Zhongzheng E. Rd., Danshui Dist, New Taipei City 25

FS98O22 Rev. 1.6 20/146 2.3. ADC Characteristics (VDD=3V, TA=25 , unless otherwise noted)℃ Table 2-3 FS98O22 ADC characteristics Symbol Para

FS98O22 Rev. 1.6 21/146 3. Memory Organization 3.1. Program Memory Structure FS98O22 has an 12bits Program Counter which is capable of addre

FS98O22 Rev. 1.6 22/146 3.3. System Special Registers The System Special Registers are designed to complete CPU Core functions, and consists

FS98O22 Rev. 1.6 23/146 3.3.2. IND and FSR Registers The IND (Indirect Addressing) register is not a physical register, but indirect addressi

FS98O22 Rev. 1.6 24/146 3.3.3. STATUS Register The STATUS register contains the arithmetic status of ALU and the RESET status. The STATUS reg

FS98O22 Rev. 1.6 25/146 3.3.4. INTE and INTF registers The INTE and INTF registers are readable and writable registers, and contain enable an

FS98O22 Rev. 1.6 26/146 Register INTF at address 06H property U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTF TMIF I2CIF ADIF E1IF

FS98O22 Rev. 1.6 27/146 3.4. Peripheral Special Registers The Peripheral Special Registers are designed for Peripheral functions, such as I/O

FS98O22 Rev. 1.6 28/146 Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power on Reset 49H LC

FS98O22 Rev. 1.6 29/146 4. Power System FS98O22 has a special power system that can supply a fixed voltage (3.6V) for CPU and ADC. FS98O22 co

FS98O22 Rev. 1.6 3/146 Contents 1. DEVICE OVERVIEW ...

FS98O22 Rev. 1.6 30/146 Table 4-1 FS98O22 power system register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

FS98O22 Rev. 1.6 31/146 Register NETE at address 1CH property U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 NETE ENVS SILB[1:0] ENLB

FS98O22 Rev. 1.6 32/146 Register NETF at address 1DH property U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 NETF ENBAND ENVDDA ENAGND E

FS98O22 Rev. 1.6 33/146 4.1. Voltage Doubler Figure 4-2 Voltage Doubler Voltage Doubler is used for generating VGG which provide input4 fo

FS98O22 Rev. 1.6 34/146 Table 4-3 Voltage Doubler operation frequency selection table M0_CK S_PCK Voltage Doubler Operation Frequency 0 0 M

FS98O22 Rev. 1.6 35/146 4.2. Voltage Regulator Figure 4-3 Voltage regulator Voltage Regulator is used for generating VDDA (3.6V). The input

FS98O22 Rev. 1.6 36/146 4.3. Analog Bias Circuit Figure 4-4 analog bias circuit Analog Bias Circuit is used to activate VB (reference VDDA)

FS98O22 Rev. 1.6 37/146 4.4. Analog Common Voltage Generator Figure 4-5 analog common voltage generator Analog Common Voltage Generator is

FS98O22 Rev. 1.6 38/146 4.5. Low Battery Comparator Figure 4-6 low battery comparator function block Low Battery Comparator is used for VDD

FS98O22 Rev. 1.6 39/146 4.6. Bandgap Voltage and Temperature Sensor Figure 4-7 Bandgap voltage and temperature sensor function block REFO i

FS98O22 Rev. 1.6 4/146 4.6 Bandgap Voltage and Temperature Sensor ...

FS98O22 Rev. 1.6 40/146 5. Clock System Table 5-1 FS98O22 clock system register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit

FS98O22 Rev. 1.6 41/146 5.1. Oscillator State Figure 5-2 FS98O22 oscillator state block Table 5-2 FS98O22 clock system register table Ther

FS98O22 Rev. 1.6 42/146 To enable the internal and external oscillators, users need to set the right values for M7_CK and M6_CK as shown in T

FS98O22 Rev. 1.6 43/146 5.3. ADC Sample Frequency FS98O22 embeds one sigma delta ADC which needs clock input to generate digital output. When

FS98O22 Rev. 1.6 44/146 5.4. Beeper Clock Table 5-10 beeper clock register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bi

FS98O22 Rev. 1.6 45/146 Table 5-14 shows the relation between clock signals and the register flags. Please see Table 5-14) Table 5-14 register

FS98O22 Rev. 1.6 46/146 5.6. Chopper Operation Amplifier Input Control Signal The OPAMP embedded in FS98O22 has a chopper function to cancel

FS98O22 Rev. 1.6 47/146 5.7. TMCLK – Timer and LCD Module Input Clock TMCLK is the clock for FS98O22 Timer and LCD Module. Users can use Tabl

FS98O22 Rev. 1.6 48/146 6. Timer Module, Watch Dog Timer and Programmable Counter Table 6-1 Timer module and watch dog timer register table A

FS98O22 Rev. 1.6 49/146 Register CTBH at address 0AH property R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X CTBH CTB[15:8] Bit7 Bit0

FS98O22 Rev. 1.6 5/146 12.2 Differential Amplifier ...

FS98O22 Rev. 1.6 50/146 Register CTCON at address 0CH property R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-X CTCON TON MUXSEL[2:0] TE FQT

FS98O22 Rev. 1.6 51/146 Register WDTCON at address 0DH property R/W-0 U-X U-X U-X U-X R/W-0 R/W-0 R/W-0 WDTCON WDTEN WTS [2:0] Bit7

FS98O22 Rev. 1.6 52/146 Register TMOUT at address 0EH property R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TMOUT TMOUT [7:0] Bit7 Bit0 Bit 7-0 TM

FS98O22 Rev. 1.6 53/146 6.1. Timer Module The Timer module has the following features: z 8-bit Timer Counter z Internal (1 MHZ) or External

FS98O22 Rev. 1.6 54/146 6.1.1. Timer module interrupt Table 6-2 timer module interrupt register table Address Name Referenced Section Bit 7

FS98O22 Rev. 1.6 55/146 6.1.2. Using Timer with External/Internal Clock The user could see the Table 6-4, 6-5, 6-6 and 6-7 to setup related r

FS98O22 Rev. 1.6 56/146 Users can use Table 6-8 to select TMCLK clock source based on M0_CK, M1_CK, M3_CK and M5_CK register flag. Table 6-8

FS98O22 Rev. 1.6 57/146 6.2. Watch Dog Timer 8 bits Counter1Watch DogTimerOscillatorWDTENMultiplexWDTA[7:0]WDTS[2:0]8 bits Counter2WDTOUTCLR

FS98O22 Rev. 1.6 58/146 6.3. Dual 16-bit Programmable Counter Address Name Content ( u mean unknown or unchanged) Reset State07H INTE GIE

FS98O22 Rev. 1.6 59/146 z Counter mode: There are two 16-bit counters (CTA and CTB) in Programmable Counter unit. Operation: 1. Clear FQTM

FS98O22 Rev. 1.6 6/146 Figure List Figure 1-1 FS98O22 pin configuration ...

FS98O22 Rev. 1.6 60/146 z Pulse Width Measurement mode: Programmable Counter could be used to measure the time when a signal holds its voltag

FS98O22 Rev. 1.6 61/146 z Frequency Measurement mode: Programmable Counter could be used to measure a signal frequency. Operation: 1. Set

FS98O22 Rev. 1.6 62/146 7. I/O Port Table 7-1 FS98O22 I/O port register table Address Name Detail on Chapter Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

FS98O22 Rev. 1.6 63/146 Register PT1 at address 20H property R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X PT1 PT1 [7:0] Bit7 Bit0 Bi

FS98O22 Rev. 1.6 64/146 property R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PT1PU PT1PU [7:0] Bit7 Bit0 Bit 7-0 PT1PU [7:0]:

FS98O22 Rev. 1.6 65/146 Register AIENB1 at address 23H property R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AIENB1 AIENB[7:0] Bit7

FS98O22 Rev. 1.6 66/146 Register PT2 at address 24H property R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X PT2 PT2 [7:0] Bit7 Bit0 B

FS98O22 Rev. 1.6 67/146 Register PT2EN at address 25H property R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PT2EN PT2EN [7:0] Bit7

FS98O22 Rev. 1.6 68/146 Register PT2PU at address 26H R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PT2PU PT2PU [7:0] Bit7 Bit0 Bi

FS98O22 Rev. 1.6 69/146 Register PT2MR at address 27H property R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PT2MR BZEN PM1EN E1M[1:0]

FS98O22 Rev. 1.6 7/146 Table List Table 1-1 Ordering Information ...

FS98O22 Rev. 1.6 70/146 Register PT3 at address 28H property R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X PT3 PT3 [7:0] Bit7 Bit0 B

FS98O22 Rev. 1.6 71/146 Register PT3EN at address 29H property R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PT3EN PT3EN [7:0] Bit7

FS98O22 Rev. 1.6 72/146 Register PT3PU at address 2AH R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PT3PU PT3PU [7:0] Bit7 Bit0 Bi

FS98O22 Rev. 1.6 73/146 Register PT3MR at address 2BH property R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PT3MR PFOEN E3M[1:0] E2M

FS98O22 Rev. 1.6 74/146 Register PT2OCB at address 37H property U-X U-X U-X R/W-1 R/W-1 U-X U-X U-X PT2OCB PT2OC[4:3] Bit7

FS98O22 Rev. 1.6 75/146 7.1. Digital I/O Port with Analog Input Channel Shared: PT1[7:0] Figure 7-1 PT1[7:0] function block GPIO Port 1 (PT

FS98O22 Rev. 1.6 76/146 Table 7-2 PT1 register table Address Name Detail on Chapter Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

FS98O22 Rev. 1.6 77/146 7.2. Digital I/O Port and External Interrupt Input : PT2[0], PT2[1], PT3[0], PT3[1] Figure 7-2 PT2[0] PT2[1] PT3[0]

FS98O22 Rev. 1.6 78/146 Table 7-3 PT2 register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value on

FS98O22 Rev. 1.6 79/146 7.3. Digital I/O Port or PDM Output : PT2[2] and PT2[5] Figure 7-3 PT2[2] function block GPIO Port 2 Bit2 (PT2[2])

FS98O22 Rev. 1.6 8/146 Table 8-1 PDM module register table ...

FS98O22 Rev. 1.6 80/146 Table 7-4 PT2 register table Address Name Detail on Chapter Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

FS98O22 Rev. 1.6 81/146 z Input: GPIO Port 2 Bit4 and Bit3 (PT2[4:3]) could be the I2C Module SCL and SDA ports or be the general I/O ports. U

FS98O22 Rev. 1.6 82/146 7.5. Digital I/O Port : PT2[6] Figure 7-5 PT2[6] function block GPIO Port 2 Bit 6 (PT2[6]) function block is shown

FS98O22 Rev. 1.6 83/146 Table 7-6 PT2 register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o

FS98O22 Rev. 1.6 84/146 7.6. Digital I/O Port or Buzzer Output : PT2[7] Figure 7-6 PT2[7] function block GPIO Port 2 Bit2 (PT2[2]) function

FS98O22 Rev. 1.6 85/146 Table 7-7 PT2[7] register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Valu

FS98O22 Rev. 1.6 86/146 8. PDM (Pulse Density Modulator) Module Please see Figure 8-1 and Figure 8-2. The GPIO port 2 bit 2 (PT2[2]) could b

FS98O22 Rev. 1.6 87/146 Figure 8-2 PDM module signal generation PDM15 PDM14 PDM13 … PDM12 If PMD1 = 0xC000H PDM out If PMD1 = 0x5000H PDM out

FS98O22 Rev. 1.6 88/146 Table 8-1 PDM module register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FS98O22 Rev. 1.6 89/146 Register PMD1H at address 30H property R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMD1H PMD1[15:8] Bit7

FS98O22 Rev. 1.6 9/146 Register List Register STATUS at address 04H ...

FS98O22 Rev. 1.6 90/146 Register PMD2H at address 30H property R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMD2H PMD2[15:8] Bit7

FS98O22 Rev. 1.6 91/146 Register PMCON at address 36H property U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 PMCON PDMEN PMCS[2:0] Bit7

FS98O22 Rev. 1.6 92/146 Table 8-2 PMD register table Address Name Detail on Chapter Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

FS98O22 Rev. 1.6 93/146 9. I2C Module (slave mode only) FS98O22 embeds a slave mode I2C module. The two pins, SCL and SDA, are used to perfor

FS98O22 Rev. 1.6 94/146 Figure 9-2 I2C module function block FORTUNE' Properties For Reference Only

FS98O22 Rev. 1.6 95/146 Table 9-1 I2C module register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FS98O22 Rev. 1.6 96/146 Register I2CSTA at address 58H property U-X U-X R/W-0 R/W-0 R/W-0 R/W-0 U-X R/W-0 I2CSTA DA P S RW BF B

FS98O22 Rev. 1.6 97/146 Register I2CBUF at address 5AH property R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 I2CBUF I2CBUF [7:0] Bit7

FS98O22 Rev. 1.6 98/146 Table 9-2 I2C register table Address Name Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value

FS98O22 Rev. 1.6 99/146 I2C data transmit operation: 1. Configure SCL and SDA pins as open-drain through the PTOCB[4:3]. 2. Set I2CEN regis